The architecture targets ring-based FHE operations and supports CKKS, BGV, and GSW, with evaluation centered on CKKS. Deep parameter sets contain 64K ring elements and roughly 1,600-bit coefficients, making one ciphertext about 25 MB.

1. assumption

   Security and correctness are parameter dependent

   parameter dependent

   CraterLake accelerates cryptographic computations chosen by the application and compiler; semantic security, numerical precision, circuit correctness, and parameter adequacy remain properties of the selected FHE scheme and parameter set.

   Supported schemes, ciphertext representation, and key switching · Energy and higher-security-parameter sensitivity

The system integrates algorithmic key-switch compression, a wide vector processor, specialized functional units, memory organization, and static compiler scheduling.

1. algorithm

   Boosted key switching

   constructed

   The boosted formulation reduces projected auxiliary key material for a deep parameter set from roughly 1.4 GB to about 50 MB, making reuse and movement feasible; KSHGen can generate half of a hint on demand and reduce resident hint storage to about 25 MB.

   Boosted key-switching algorithm and data reduction · Vector organization, transpose network, residue conversion, and key-switch generation
2. architecture

   Wide-vector datapath

   constructed

   A 2,048-lane uniprocessor, fixed transpose network, and specialized residue-conversion and key-switch-generation units expose the parallelism and data transforms used by large polynomial operations.

   Vector organization, transpose network, residue conversion, and key-switch generation
3. method

   Compiler-directed scheduling

   implemented

   The compiler schedules operations, reuses data, overlaps or decouples movement from computation, and chains kernels so intermediate values need not repeatedly traverse costly memory paths.

   Compiler scheduling, chaining, and data movement

The paper claims practical acceleration of unbounded-depth FHE and reports advantages in latency and energy over its evaluated CPU and F1+ baselines.

1. claim

   Refresh enables deep workloads

   supported by evaluation

   Unlike accelerators restricted to circuits within a fixed noise budget, the represented design includes bootstrapping and therefore runs the evaluated deep ResNet, LSTM, and other workloads without a bounded-depth architectural ceiling.

   FHE depth barrier and CraterLake contributions · Deep-workload latency and baseline comparisons
2. claim

   Large modeled speedups on deep workloads

   measured in model

   Across the paper's deep benchmark set, CraterLake reports an 11.2x geometric-mean speedup over the scaled F1+ baseline and 4,611x over the CPU baseline; reported examples include 249.45 ms for ResNet-20 and 3.91 ms for packed bootstrapping.

   Deep-workload latency and baseline comparisons
3. claim

   Energy advantage

   estimated

   The modeled deep-workload evaluation reports about 18x lower energy and about 201x higher performance per joule than scaled F1+.

   Energy and higher-security-parameter sensitivity

The evidence combines RTL synthesis and cycle-accurate architectural simulation with a 32-core AMD Threadripper CPU and a scaled improved F1+ design as baselines.

1. evidence

   Security-parameter sensitivity

   sensitivity analysis

   Relative to the base 80-bit parameter evaluation, the paper reports a 1.36x geometric-mean slowdown at 128-bit security and 2.60x at 200-bit security, the latter using a larger 128K-element hardware configuration.

   Energy and higher-security-parameter sensitivity

The results establish a simulated and synthesized architecture under selected cryptographic parameters and workloads, not universal FHE performance or deployment readiness.

1. limitation

   No fabricated-silicon measurement

   evidence boundary

   Area, power, timing, energy, and workload latency are derived from synthesis and simulation rather than a fabricated chip, so manufacturing and deployment effects remain unevaluated.

   RTL synthesis, physical estimates, and simulation method
2. limitation

   Benchmark and baseline dependence

   benchmark bounded

   Speedups depend on the selected workloads, parameter sets, compiler schedules, and scaled comparison designs; shallow workloads sometimes narrow or reverse the advantage over F1+.

   Deep-workload latency and baseline comparisons · Energy and higher-security-parameter sensitivity